1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device, more specifically, to a method of simultaneously forming the diffusion areas thereof in different diffusion depths.
2. Description of the Prior Art
In general, a semiconductor integrated circuit (IC) comprises an input/output interface circuit for receiving an external signal and outputting a signal to external circuits and an internal circuit having other functions such as logical operations.
The input/output interface circuit and the internal circuit are respectively composed of various elements, such as a transitor; such a transistor, for example, and other elements of both the interface circuit and the internal circuit are generally formed simultaneously by the same manufacturing process.
However, a transistor which receives an input signal from the outside, i.e., an external source, often receives external noise, for example, an extremly high voltage, and therefore it is desired for such an element to have a withstand voltage, i.e., breakdown voltage (those terms being used synonymously throughout), higher than that of those elements employed only in the internal circuit so that it can be reliably prevented from breakdown due to such external noise.
In the case of some ICs, the input/output interface circuit often operates at a high voltage, for example, 5 V, while the internal circuit operates at a low voltage, for example, 2 V. In this case, it is required also for a transistor employed in the input/output interface circuit to have a withstand voltage higher than that of a transistor employed solely in the internal circuit.
Such requirement can be met, for example, in the case of a bipolar transistor by providing a large difference between the depth of its base region and that of its emitter region.
Therefore, a transistor having a withstand voltage higher than that of a transistor in the internal circuit can be obtained by, for example, making the emitter region of the transistor in the input interface shallower than that of a transistor employed in the internal circuit while keeping the depth of the base regions of such transistors the same.
An IC comprising transistors of different junction depths can be manufactured using a conventional diffusion method or ion implantation. If the diffusion method is employed, each of the emitter diffusion and the base diffusion is carried out twice. For this reason, the diffusion method introduces an increase in the steps of the manufacturing processes.
If the ion implantation method is employed, the junction depth can be differentiated in a single ion implantation process by using a mask of predetermined, different thicknesses. However, direct ion implantation on the semiconductor surface damages the crystal structure of the semiconductor material, thus increasing leakage current defects.
Japanese laid-open patent specification No. 54-154287 discloses a method of manufacturing an IC wherein predetermined impurities are implanted into the silicon semiconductor substrate by the ion implantation method through an insulating film having selectively different thicknesses, for example, a silicon oxide insulating film, and simultaneously the semiconductor regions of different resistance values and junction depths are formed. According to this method, an IC comprising transistors of different junction depths can be realized without increases in the manufacturing processes but, as mentioned above, an increase of the leakage current of the transistor can result. Damage to the crystalline structure of the substrate at the area where ions are implanted via the silicon oxide film is alleviated. However, since oxygen atoms in the silicon oxide film are released by the impact of the bombarding ions on, and moving through the silicon oxide film, a defect is created. Japanese laid-open patent specifications Nos. (51-123071, 51-147969) disclose a method where the impurity doped polycrystalline silicon layer is caused to have selectively different thicknesses whereby junctions of different depths are formed.
Moreover, Japanese laid-open patent specification No. (52-150962) discloses a method where a single crystalline thin film which has selectively different thicknesses and different etching characteristic, for example, Ga0.7Al0.3A.sub.s is formed on the semiconductor substrate, for example, GaAs; impurities for doping the substrate are introduced by the diffusion or the ion implantation methods through the thin film, and thereafter the thin film is removed by an etching method.